An Efficient Low-Power Buffer Insertion with Time and Area Constraints

Technology scaling has resulted in interconnect delay increasing significantly. Buffer-insertion is a wellknown technique to reduce wire delays of critical signal nets in a circuit. However, the power consumption of buffers has become a critical concern with the increase of the number of buffers. Thanks to a genetic-based algorithm, our work addresses the interconnect delay problem while meeting power and area constraints. Key-Words: Submicron interconnections, buffer insertion, low-power design, area and time constraints